The Design and Implementation of 32-Bit Arithmetic Divider and Multiplier using Single Stage Design

Abstract

Multiplier and divider are the most important parts of any arithmetic unit. Design parameters area, speed and power consumption are main constraints in designing multiplier and divider. In the proposed work we will use single stage design technique to design multiplier and divider. In single stage implementation design the complex logic operations which consist of various multiple numbers of stages are converted into single stage implementation by using single stage design the many short delays are compensated by a single large delay and performance of the design will improve. Xilinx software is use for coding and simulation will be done using Questa Sim simulator and overall design will be implemented on vertex 5 FPGA.