The DESIGN AND ANALYSIS OF HIGH PERFORMANCE RISC PROCESSOR USING HYPERPIPELINING TECHNIQUE

Abstract

The paper proposes RISC processor with floating point arithmetic for high speed and low power consumption .It is having five stage pipelining which is designed using VHDL. Number of instruction which are designed for this processors. We use 5-stage pipelining which involves instruction fetch module, instruction decode, module, execution module, memory i/o and write block.